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data sheet 1 1.0 www.infineon.com 2016-09-08 TLE94106EL features ? six half bridge power outputs ? very low power consumption in sleep mode ? 3.3v / 5v compatible inputs with hysteresis ? all outputs with overload and short circuit protection ? independently diagnosable outp uts (overcurrent, open load) ? open load diagnostics in on-state for all high-side and low-side ? outputs with selectable open load thresholds (hs1, hs2) ? 16-bit standard spi interface with daisy chain and in-frame response capability for control and diagnosis ? fast diagnosis with the global error flag ? pwm capable outputs for fre quencies 80hz, 100hz and 200hz with 8-bit duty cycle resolution ? overtemperature pre-warning and protection ? over- and undervoltage lockout ? cross-current protection applications ?hvac flap dc motors ? monostable and bistable relays ? side mirror x-y adjustment and mirror fold ?leds description the TLE94106EL is a protected six-fold half-bridge driver designed especially for automotive motion control applications such as heating, ventilat ion and air conditioning (hvac) flap dc motor control. it is part of a larger family offering half-bridge dr ivers from three outputs to twelve ou tputs with direct interface or spi interface. the half bridge drivers are designed to drive dc motor loads in sequ ential or parallel operation. operation modes forward (cw), reverse (ccw), br ake and high impedance are controll ed from a 16-bit spi interface. it offers diagnosis features such as short circuit, open load, power supply fa ilure and overtemperature detection. in combination with its lo w quiescent current, this device is a ttractive among others for automotive applications. the small fine pitch exposed pad pack age, pg-ssop-24, provides good thermal performance and reduces pcb-board space and costs.
data sheet 2 1.0 2016-09-08 TLE94106EL type package marking TLE94106EL pg-ssop-24 TLE94106EL table 1 product summary normal operating voltage v s 5.5 ... 18 v extended operating voltage v s(ext) 18 ... 20 v logic supply voltage v dd 3.0 ... 5.5 v maximum supply voltage for load dump protection v s(ld) 40 v minimum overcurrent threshold i sd 0.9 a maximum on-state path resistance at t j = 150c r dson(total)_hsx+lsy 1.8 + 1.8 ? typical quiescen t current at t j = 85c i sq 0.1 a maximum spi access frequency f sclk 5mhz
data sheet 3 1.0 2016-09-08 TLE94106EL 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 voltage and current definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 general product characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 reset behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 half-bridge outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1.1 half-bridge operation with pwm enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1.1.1 inductive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1.1.2 led mode (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 protection & diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2.1 short circuit of output to supply or ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.2 cross-current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.3 temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.4 overvoltage and undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2.4.1 v s undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2.4.2 v s overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2.4.3 v dd undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2.5 open load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 spi description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1.1 global error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.2 global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1.3 spi protocol error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2 spi with independent slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3 daisy chain operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.4 status register change during spi communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.5 spi bit mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.6 spi control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.6.1 control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.7 spi status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table of contents
data sheet 4 1.0 2016-09-08 TLE94106EL 7.7.1 status register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.1 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.2 thermal application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.3 emc enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
data sheet 5 1.0 2016-09-08 TLE94106EL pin configuration 1 pin configuration 1.1 pin assignment figure 1 pin configuration TLE94106EL 1.2 pin definitions and functions pin symbol function 1 gnd ground. all ground pins should be externally connected together. 2out 1 power half-bridge 1 3out 5 power half-bridge 5 4 n.c. not connected. this pin should either be left open or terminated to ground. 5 sdi serial data input with internal pull down 6 vdd logic supply voltage 7 sdo serial data output 8 en enable with internal pull-down; places de vice in standby mode by pulling the en line low 9 n.c. not connected. this pin must either be left open or terminated to ground 10 out 6 power half-bridge 6 11 out 4 power half-bridge 4 12 gnd ground. all ground pins should be externally connected together. n.c. out 2 nc vs2 sclk csn n.c. sdo en n.c. out 6 out 4 gnd gnd out 1 out 5 n.c. sdi vdd n.c. vs1 nc out 3 n.c. 18 17 16 15 14 13 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12
data sheet 6 1.0 2016-09-08 TLE94106EL pin configuration 13 n.c. not connected. this pin should either be left open or terminated to ground (e.g. for layout compatib ility with tle94112el, tle94110el or tle94108el). 14 out 3 power half-bridge 3 15 n.c. not connected. this pin should either be left open or terminated to ground. 16 vs1 main supply voltage for power half bridge s. vs1 should be externally connected to vs2. 17 n.c. not connected. this pin should either be left open or terminated to ground. 18 n.c. not connected. this pin should either be left open or terminated to ground. 19 csn chip select not input with internal pull up 20 sclk serial clock input with internal pull down 21 vs2 main supply voltage for power half bridge s. vs1 should be externally connected to vs2. 22 n.c. not connected. this pin should either be left open or terminated to ground. 23 out 2 power half-bridge 2 24 n.c. not connected. this pin should either be left open or terminated to ground (e.g. for layout compatib ility with tle94112el, tle94110el or tle94108el). edp - exposed die pad; for cooling and emc pu rposes only - not usable as electrical ground. electrical gr ound must be provided by pins 1,12. 1) 1) the exposed die pad at the bottom of the package allows better heat dissipation from the device via the pcb. the exposed pad (ep) must be either left open or connected to gnd. it is recommended to connect ep to gnd for best emc and thermal performance. pin symbol function
data sheet 7 1.0 2016-09-08 TLE94106EL block diagram 2 block diagram figure 2 block diagram tle9 4106el (spi interface) sclk en csn sdi sdo bias & monitor undervoltage & overvoltage monitor vdd error detection charge pump open load detection current control high- side driver low-side driver shor t to battery detection temp sensor current contr ol short to batter y detection high-side driver low-side driver short to batter y detection temp sensor open load detection current control short to battery detection high -side driver low-side driver short to battery detection temp sensor open load detection cur r ent control short to battery detection high -side driver low-side driver short to battery detection temp sensor current control short to battery detection out 5 out 4 out 3 out 2 out 1 open load detection current control short to battery detection low-side driver short to battery detection temp sensor open load detection current control short to batter y detection high -side driver low-side driver short to batter y detection temp sensor current control short to battery detection high -side driver low-side driver short to battery detection temp sensor current control shor t to batter y detection high -side driver low- side driver short to battery detection temp sensor current control short to battery detection temp sensor high -side driver low-side driver power driver temp sensor power stage out 6 logic control & latch spi interface six-fold half bridge driver spi interface open load detection short to ground detection overtemperature detection open load detection short to battery detection overtemperature detection gnd gnd vs1 vs2 pwm generator
data sheet 8 1.0 2016-09-08 TLE94106EL block diagram 2.1 voltage and current definition figure 3 shows terms used in this da tasheet, with associated convention for positive values. figure 3 voltage and current definition spi interface driver v dd v sd o v s i s1 vdd sdo sdi csn vs 1 v sd i v csn v sc l k sclk gnd i gnd v en en out x i outx v dslsx v dshsx i csn i sd i i sc l k i sd o i en i dd i s2 vs 2 gnd i gnd
data sheet 9 1.0 2016-09-08 TLE94106EL general product characteristics 3 general product characteristics 3.1 absolute maximum ratings notes 1. stresses above the ones listed he re may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2 absolute maximum ratings 1) t j = -40c to +150c 1) not subject to production test, specified by design parameter symbol values unit note or test condition number min. typ. max. voltages supply voltage v s -0.3 ? 40 v v s = v s1 = v s2 p_4.1.1 supply voltage slew rate | dv s /dt | ??10v/s v s increasing and decreasing 1) p_4.2.2 power half-bridge output voltage v out -0.3 ? 40 v 0 v < v out < v s p_4.1.2 logic supply voltage v dd -0.3 ? 5.5 v 0 v < v s < 40 v p_4.1.3 logic input voltages (sdi, sclk, csn, en) v sdi , v sclk , v csn , v en -0.3 ? vdd v 0 v < v s < 40 v 0 v < v dd < 5.5v p_4.1.4 logic output voltage (sdo) v sdo -0.3 ? vdd v 0 v < v s < 40 v 0 v < v dd < 5.5v p_4.1.5 currents continuous supply current for v s1 i s1 0?1.5a? p_4.1.6 continuous supply current for v s2 i s2 0?1.5a? p_4.1.7 current per gnd pin i gnd 0?2.0a? p_4.1.14 output currents i out -2.0 ? 2.0 a ? p_4.1.15 temperatures junction temperature t j -40 ? 150 c ? p_4.1.8 storage temperature t stg -50 ? 150 c ? p_4.1.9 esd susceptibility esd susceptibility outn and vsx pins versus gnd. all other pins grounded. v esd -8 ? 8 kv jedec hbm 1)2) 2) esd susceptibility, ?jedec hbm? according to ansi/ esda/ jedec js001 (1.5 k ? , 100pf) p_4.1.10 esd susceptibility all pins v esd -2 ? 2 kv jedec hbm 1)2) p_4.1.11 esd susceptibility all pins v esd -500 ? 500 v cdm 1)3) 3) esd susceptibility, charged device model ?cdm? according jedec jesd22-c101 p_4.1.12 esd susceptibility corner pins v esd -750 ? 750 v cdm 1)3) p_4.1.13
data sheet 10 1.0 2016-09-08 TLE94106EL general product characteristics 2. integrated protection functions are designed to preven t ic destruction under fault conditions described in the data sheet. fault conditions are cons idered as ?outside? normal operatin g range. protection functions are not designed for continuous repetitive operation.
data sheet 11 1.0 2016-09-08 TLE94106EL general product characteristics 3.2 functional range note: within the normal functional range the ic oper ates as described in the circuit description. the electrical characteristic s are specified within the conditions given in the related electrical characteristics table. table 3 functional range parameter symbol values unit note or test condition number min. typ. max. supply voltage range for normal operation v s(nor) 5.5 ? 18 v ? p_4.2.1 extended supply voltage range v s(ext) 18 ? 20 v 1)2) 1) not subject to production test, specified by design. 2) in the extended supply range, the device is still func tional. however, deviations of the specified electrical characteristics are possible. p_4.2.7 logic supply voltage range for normal operation v dd 3.0 ? 5.5 v ? p_4.2.3 logic input voltages (sdi, sclk, csn, en) v sdi , v sclk , v csn , v en -0.3 ? 5.5 v ? p_4.2.4 junction temperature t j -40 ? 150 c p_4.2.5
data sheet 12 1.0 2016-09-08 TLE94106EL general product characteristics 3.3 thermal resistance table 4 thermal resistance TLE94106EL parameter symbol values unit note or test condition number min. typ. max. junction to case, t a = -40c r thjc_cold ?7?k/w 1) junction to case, t a = 85c r thjc_hot ?9?k/w 1) junction to ambient, t a = -40c (1s0p, minimal footprint) r thja_cold_ min ?80?k/w 1) 2) 1) not subject to production test, specified by design. 2) specified r thja value is according to jedec jesd51-2, -3 at natura l convection on fr4 1s0p board; the product (chip + package) was simulated on a 76.2 x 114.3 x 1.5mm board wi th minimal footprint copper area and 35m thickness. ta = -40c, each channel dissipates 0.2w. ta = 85c, each channel dissipates 0.135w. junction to ambient, t a = 85c (1s0p, minimal footprint) r thja_hot_m in ?85?k/w 1) 2) junction to ambient, t a = -40c (1s0p, 300mm2 cu) r thja_cold_3 00 ?51?k/w 1) 3) 3) specified r thja value is according to jedec jesd51-2, -3 at natura l convection on fr4 1s0p board; the product (chip + package) was simulated on a 76.2 x 114.3 x 1.5mm board wi th additional cooling of 3 00mm2 copper area and 35m thickness. ta = -40c, each channel dissipates 0.2w. ta = 85c, each channel dissipates 0.135w. junction to ambient, t a = 85c (1s0p, 300mm2 cu) r thja_hot_30 0 ?58?k/w 1) 3) junction to ambient, t a = -40c (1s0p, 600mm2 cu) r thja_cold_6 00 ?51?k/w 1) 4) junction to ambient, t a = 85c (1s0p, 600mm2 cu) r thja_hot_60 0 ?58?k/w 1) 4) 4) specified r thja value is according to jedec jesd51-2, -3 at natura l convection on fr4 1s0p board; the product (chip + package) was simulated on a 76.2 x 114.3 x 1.5mm board wi th additional cooling of 6 00mm2 copper area and 35m thickness. ta = -40c, each channel dissipates 0.2w. ta = 85c, each channel dissipates 0.135w. junction to ambient, t a = -40c (2s2p) r thja_cold_2 s2p ?35?k/w 1) 5) 5) specified r thja value is according to jedec jesd51-2, -3 at natura l convection on fr4 2s2p board; the product (chip + package) was simulated on a 76.2 x 114.3 x 1.5mm board with two inner copper layers ( 4 x 35m cu). ta = -40c, each channel dissipates 0.2w. ta = 85c, each channel dissipates 0.135w. junction to ambient, t a = 85c (2s2p) r thja_hot_2s 2p ?44?k/w 1) 5)
data sheet 13 1.0 2016-09-08 TLE94106EL general product characteristics 3.4 electrical characteristics table 5 electrical characteristics, v s =5.5 v to 18 v, v dd = 3.0v to 5.5v, t j = -40c to +150c, en= high, i outn = 0 a; typical values refer to v dd = 5.0 v, v s = 13.5 v and t j = 25 c unless otherwise specified; all voltages with respect to ground , positive current flow ing into pin (unless otherwise specified) parameter symbol values unit note or test condition number min. typ. max. current consumption, en = gnd supply quiescent current i sq ? 0.5 2 a -40c t j 85c p_4.4.1 logic supply quiescent current i dd_q ? 0.1 1 a -40c t j 85c p_4.4.2 total quiescent current i sq + i dd_q ? 0.6 3 a -40c t j 85c p_4.4.3 current consumption, en=high supply current i s ? 0.5 1 ma power drivers and power stages are off p_4.4.4 supply current i s_hson ? 4.5 9 ma all high-sides on 1) p_4.4.101 logic supply current i dd ?1.53maspi not active p_4.4.5 logic supply current i dd_run ?5?maspi 5mhz 3) p_4.4.6 total supply current i s + i dd_run ?5.5?maspi 5mhz 3) p_4.4.7 over- and undervoltage lockout undervoltage switch on voltage threshold v uv on 4.25 ? 5.25 v v s increasing p_4.4.8 undervoltage switch off voltage threshold v uv off 4?5.0v v s decreasing p_4.4.9 undervoltage switch on/off hysteresis v uv hy ?0.25?v v uv on - v uv off 3) p_4.4.10 overvoltage switch off voltage threshold v ov off 21 ? 25 v v s increasing p_4.4.11 overvoltage switch on voltage threshold v ov on 20 ? 24 v v s decreasing p_4.4.12 overvoltage switch on/off hysteresis v ov hy ?1?v v ov off - v ov on 3) p_4.4.13 v dd power-on-reset v dd por 2.40 2.70 2.90 v v dd increasing p_4.4.14 v dd power-off-reset v dd poffr 2.35 2.65 2.85 v v dd decreasing p_4.4.15 v dd power on/off hysteresis v dd por hy ?0.05?v v dd por - v dd poffr 3) p_4.4.98 static drain-source on-resistance (high-side or low-side) high-side or low-side r dson (all outputs) r dson_hb_25c ? 850 1200 m ? i out = 0.5 a; t j = 25 c p_4.4.16 high-side or low-side r dson (all outputs) r dson_hb_150 c ? 1400 1800 m ? i out = 0.5 a; t j = 150 c p_4.4.17
data sheet 14 1.0 2016-09-08 TLE94106EL general product characteristics high-side r dson (hs1 and hs2 in led mode) r dson_hi_hb_ 25c ? 950 1300 m ? 2) i out = 0.1 a; t j = 25 c p_4.4.18 high-side r dson (hs1 and hs2 in led mode) r dson_hi_hb_ 150c ? 1500 2000 m ? 2) i out = 0.1 a; t j = 150 c p_4.4.19 output protection and diagnosis of high-s ide (hs) channels of half-bridge output hs overcurrent shutdown threshold i sd_hs -1.4 -1.1 -0.9 a see figure 7 p_4.4.89 difference between shutdown and limit current i lim_hs - i sd_hs -1.2 -0.6 0 a 3) |i lim_hs | |i sd_hs| see figure 7 p_4.4.21 overcurrent shutdown filter time t dsd_hs 15 19 23 s 3) p_4.4.22 open load detection current i old1_hs -15 -8 -3 ma - p_4.4.23 open load detection filter time t old1_hs 2000 3000 4000 s 3) p_4.4.24 open load detection current for led mode (hs1 & hs2) i old2_hs1,2 -3.2 -2 -0.5 ma bit ol_sel_hs1 = 1, ol_sel_hs2 = 1 p_4.4.25 open load detection filter time for led mode (hs1 & hs2) t old2_hs1,2 100 200 300 s bit ol_sel_hs1 = 1, ol_sel_hs2 = 1; 3) p_4.4.26 output protection and diagnosis of low-side (ls) channels of half-bridge output ls overcurrent shutdown threshold i sd_ls 0.9 1.1 1.4 a figure 8 p_4.4.104 difference between shutdown and limit current i lim_ls - i sd_ls 00.61.2a 3) i lim_ls i sd_ls figure 8 p_4.4.28 overcurrent shutdown filter time t dsd_ls 15 19 23 s 3) p_4.4.29 open load detection current i old_ls 3815ma- p_4.4.30 open load detection filter time t old_ls 2000 3000 4000 s 3) p_4.4.31 outputs out(1...n) leakage current hs leakage current in off state i qlhn_nor -2 -0.5 ? a v outn = 0v ; en=high p_4.4.32 hs leakage current in off state i qlhn_sle -2 -0.5 ? a v outn = 0v; en=gnd p_4.4.33 ls leakage current in off state i qlln_nor ?0.52a v outn = v s ; en=high p_4.4.34 ls leakage current in off state i qlln_sle ?0.52a v outn = v s ; en=gnd p_4.4.35 output switching times. see figure 9 and figure 10 . slew rate of high-side and low- side outputs d vout / dt 0.1 0.45 0.75 v/s resistive load = 100 ? ; v s =13.5v 4) p_4.4.36 table 5 electrical characteristics, v s =5.5 v to 18 v, v dd = 3.0v to 5.5v, t j = -40c to +150c, en= high, i outn = 0 a; typical values refer to v dd = 5.0 v, v s = 13.5 v and t j = 25 c unless otherwise specified; all voltages with respect to ground , positive current flow ing into pin (unless otherwise specified) (cont?d) parameter symbol values unit note or test condition number min. typ. max.
data sheet 15 1.0 2016-09-08 TLE94106EL general product characteristics output delay time high side driver on t donh 52035sresistive load = 100 ? to gnd p_4.4.37 output delay time high side driver off t doffh 15 45 75 s resistive load = 100 ? to gnd p_4.4.38 output delay time low side driver on t donl 52035sresistive load = 100 ? to vs p_4.4.39 output delay time low side driver off t doffl 15 45 75 s resistive load = 100 ? to vs p_4.4.40 cross current protection time, high to low t dhl 100 130 160 s resistive load = 100 ? 3) p_4.4.41 cross current protection time, low to high t dlh 100 130 160 s resistive load = 100 ? 3) p_4.4.42 input interface: logic input en high-input voltage v enh 0.7 * v dd ?? v ? p_4.4.43 low-input voltage v enl ? ? 0.3 * v dd v? p_4.4.44 hysteresis of input voltage v enhy ? 500 ? mv 3) p_4.4.45 pull down resistor r pd_en 20 40 70 k ? v en = 0.2 x v dd p_4.4.46 spi frequency maximum spi frequency f spi,max ??5.0mhz 3) 5) p_4.4.47 spi interface: delay time from en rising edge to first data in setup time t set ? ? 150 s 3) see figure 14 p_4.4.48 spi interface: input interface, logic inputs sdi, sclk, csn h-input voltage threshold v ih 0.7 * v dd ?? v ? p_4.4.50 l-input voltage threshold v il ? ? 0.3 * v dd v? p_4.4.51 hysteresis of input voltage v ihy ? 500 ? mv 3) p_4.4.52 pull up resistor at pin csn r pu_csn 30 50 80 k ? v csn = 0.7 x v dd p_4.4.53 pull down resistor at pin sdi, sclk r pd_sdi, r pd_sclk 20 40 70 k ? v sdi , v sclk = 0.2 x v dd p_4.4.54 input capacitance at pin csn, sdi or sclk c i ?1015pf0v < v dd < 5.25v 3) p_4.4.55 input interface, logic output sdo h-output voltage level v sdoh v dd - 0.4 v dd - 0.2 ?v i sdoh = -1.6 ma p_4.4.56 table 5 electrical characteristics, v s =5.5 v to 18 v, v dd = 3.0v to 5.5v, t j = -40c to +150c, en= high, i outn = 0 a; typical values refer to v dd = 5.0 v, v s = 13.5 v and t j = 25 c unless otherwise specified; all voltages with respect to ground , positive current flow ing into pin (unless otherwise specified) (cont?d) parameter symbol values unit note or test condition number min. typ. max.
data sheet 16 1.0 2016-09-08 TLE94106EL general product characteristics l-output voltage level v sdol ?0.20.4v i sdol = 1.6 ma p_4.4.57 tri-state leakage current i sdolk -1 ? 1 a v csn = v dd ; 0v < v sdo < v dd p_4.4.58 tri-state input capacitance c sdo ?1015pf 3) p_4.4.59 data input timing. see figure 15 and figure 17 . sclk period t pclk 200 ? ? ns 3) p_4.4.60 sclk high time t sclkh 0.45 * t pclk ? 0.55 * t pclk ns 3) p_4.4.61 sclk low time t sclkl 0.45 * t pclk ? 0.55 * t pclk ns 3) p_4.4.62 sclk low before csn low t bef 125 ? ? ns 3) p_4.4.63 csn setup time t lead 250 ? ? ns 3) p_4.4.64 sclk setup time t lag 250 ? ? ns 3) p_4.4.65 sclk low after csn high t beh 125 ? ? ns 3) p_4.4.66 sdi setup time t sdi_setup 30 ? ? ns 3) p_4.4.67 sdi hold time t sdi_hold 30 ? ? ns 3) p_4.4.68 input signal rise time at pin sdi, sclk, csn t rin ??50ns 3) p_4.4.69 input signal fall time at pin sdi, sclk, csn t fin ??50ns 3) p_4.4.70 delay time from en falling edge to standby mode t dmode ??8s 3) p_4.4.71 minimum csn high time t csnh 5??s 3) p_4.4.72 data output timing. see figure 15 . sdo rise time t rsdo ?3080nsc load = 40pf 3) p_4.4.73 sdo fall time t fsdo ?3080nsc load = 40pf 3) p_4.4.74 sdo enable time after csn falling edge t ensdo ? ? 75 ns low impedance 3) p_4.4.75 sdo disable time after csn rising edge t dissdo ??75nshigh impedance 3) p_4.4.76 duty cycle of incoming clock at sclk duty sclk 45 ? 55 % 3) p_4.4.77 sdo valid time for v dd = 3.3v t vasdo3 ?7095ns v sdo < 0.2 x v dd v sdo > 0.8 x v dd c load = 40pf 3) p_4.4.78 table 5 electrical characteristics, v s =5.5 v to 18 v, v dd = 3.0v to 5.5v, t j = -40c to +150c, en= high, i outn = 0 a; typical values refer to v dd = 5.0 v, v s = 13.5 v and t j = 25 c unless otherwise specified; all voltages with respect to ground , positive current flow ing into pin (unless otherwise specified) (cont?d) parameter symbol values unit note or test condition number min. typ. max.
data sheet 17 1.0 2016-09-08 TLE94106EL general product characteristics sdo valid time for v dd = 5v t vasdo5 ?5065ns v sdo < 0.2 x v dd v sdo > 0.8 v dd c load = 40pf 3) p_4.4.79 thermal warning & shutdown thermal warning junction temperature t jw 120 140 170 c see figure 11 3) p_4.4.80 thermal shutdown junction temperature t jsd 150 175 200 c see figure 11 3) p_4.4.81 thermal comparator hysteresis t jhys ?5?c 3) p_4.4.82 ratio of sd to w temperature t jsd / t jw 1.05 1.20 ? ? 3) p_4.4.83 1) i s_hson does not include the load current 2) hs1, respectively hs2, is set to led mode by setting ol_sel_hs1 bit to 1, respectively ol_sel_hs2 bit to 1 3) not subject to production test, specified by design 4) measured for 20% - 80% of v s . 5) not applicable in daisy chain configuration table 5 electrical characteristics, v s =5.5 v to 18 v, v dd = 3.0v to 5.5v, t j = -40c to +150c, en= high, i outn = 0 a; typical values refer to v dd = 5.0 v, v s = 13.5 v and t j = 25 c unless otherwise specified; all voltages with respect to ground , positive current flow ing into pin (unless otherwise specified) (cont?d) parameter symbol values unit note or test condition number min. typ. max.
data sheet 18 1.0 2016-09-08 TLE94106EL characterization results 4 characterization results performed on 7 devices from 2 lo ts, over operating temperature an d nominal/extended supply range. typical performance characteristics supply quiescent current supply current logic supply quiescent current logic supply current \ 0.1 0.4 0.9 1.4 1.9 2.4 2.9 3.4 -50 -30 -10 10 30 50 70 90 110 130 150 isq [ua] junction temperature [c] p_4.4.1 vs=5.5v vs=13.5v vs=18v vs=19v vs=21 0 50 100 150 200 250 300 -50-30-101030507090110130150 is[ua] junction temperature [c] p_4.4.4 vs=5.5v vs=13.5v vs=18v vs=19v vs=21v -0.1 0 0.1 0.2 0.3 0.4 0.5 -50-30-101030507090110130150 idd_q[ua] junction temperature [c] p_4.4.2 vs=5.5v vs=13.5v vs=18v vs=19v vs=21v 0.74 0.75 0.76 0.77 0.78 0.79 -50-30-101030507090110130150 idd[ma] junction temperature [c] p_4.4.5 vs=5.5v vs=13.5v vs=18v vs=19v vs=21v
data sheet 19 1.0 2016-09-08 TLE94106EL characterization results hs static drain-source on-resistance l s static drain-source on-resistance hs static drain-source on-resistance vs = 13.5v and vdd = 5v ls static drain-source on-resistance vs = 13.5v and vdd = 5v 600 700 800 900 1000 1100 1200 1300 1400 1500 -50 -30 -10 10 30 50 70 90 110 130 150 rdson_hs [m ? ] junction temperature [c] p_4.4.16 and p_4.4.17 vs=5.5v vs=13.5v vs=18v vs=19v vs=21v 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 -50 -30 -10 10 30 50 70 90 110 130 150 rdson_ls [m ? ] junction temperature [c] p_4.4.16 and p_4.4.17 vs=5.5v vs=13.5v vs=18v vs=19v vs=21v 600 700 800 900 1000 1100 1200 1300 1400 1500 -50 -30 -10 10 30 50 70 90 110 130 150 rdson_hs [m ? ] junction temperature [c] p_4.4.16 and p_4.4.17 out1 out2 out3 out4 out5 out6 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 -50 -30 -10 10 30 50 70 90 110 130 150 rdson_ls [m ? ] junction temperature [c] p_4.4.16 and p_4.4.17 out1 out2 out3 out4 out5 out6
data sheet 20 1.0 2016-09-08 TLE94106EL characterization results slew rate on of high-side outputs slew rate on of low-side outputs slew rate off of high-side outputs s lew rate off of low-side outputs 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 -50-30-101030507090110130150 dvout/ dt [v/us] junction temperature [c] p_4.4.36 vs=5.5v vs=13.5v vs=18v vs=19v vs=21v 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 -50-30-101030507090110130150 dvout/ dt [v/us] junction temperature [c] p_4.4.36 vs=5.5v vs=13.5v vs=18v vs=19v vs=21v 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 -50 -30 -10 10 30 50 70 90 110 130 150 dvout/ dt [v/us] junction temperature [c] p_4.4.36 vs=5.5v vs=13.5v vs=18v vs=19v vs=21v 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 -50-30-101030507090110130150 dvout/ dt [v/us] junction temperature [c] p_4.4.36 vs=5.5v vs=13.5v vs=18v vs=19v vs=21v
data sheet 21 1.0 2016-09-08 TLE94106EL characterization results hs overcurrent shutdown threshold l s overcurrent shutdown threshold undervoltage switch on voltage threshold u ndervoltage switch off voltage threshold -1200 -1180 -1160 -1140 -1120 -1100 -1080 -1060 -1040 -50-30-101030507090110130150 isd_hs [ma] junction temperature [c] p_4.4.89 vs=5.5v vs=13.5v vs=18v vs=19v vs=21v 1040 1060 1080 1100 1120 1140 1160 1180 1200 -50 -30 -10 10 30 50 70 90 110 130 150 isd_ls [ma] junction temperature [c] p_4.4.104 vs=5.5v vs=13.5v vs=18v vs=19v vs=21v 4.65 4.7 4.75 4.8 4.85 4.9 -50-30-101030507090110130150 vuv_on [v] junction temperature [c] p_4.4.8 vdd=3v vdd=5v vdd=5.5v 4.5 4.55 4.6 4.65 4.7 4.75 4.8 -50-30-101030507090110130150 vuv_off [v] junction temperature [c] p_4.4.9 vdd=3v vdd=5v vdd=5.5v
data sheet 22 1.0 2016-09-08 TLE94106EL characterization results overvoltage switch on voltage threshold o vervoltage switch off voltage threshold vdd power-on-reset and vdd power-off-reset 21.8 21.9 22 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 -50-30-101030507090110130150 vov_on [v] junction temperature [c] p_4.4.12 vdd=3v vdd=5v vdd=5.5v 22.7 22.8 22.9 23 23.1 23.2 23.3 23.4 23.5 23.6 -50-30-101030507090110130150 vov_off [v] junction temperature [c] p_4.4.11 vdd=3v vdd=5v vdd=5.5v 2.58 2.60 2.62 2.64 2.66 2.68 2.70 2.72 -50-30-101030507090110130150 vdd threshold [v] junction temperature [c] p_4.4.14 and p_4.4.15 vdd por vdd poffr
data sheet 23 1.0 2016-09-08 TLE94106EL general description 5 general description 5.1 power supply the TLE94106EL has two power supply inputs, v s and v dd . the half bridge outputs are supplied by v s , which is connected to the 12v au tomotive supply rail. v dd is used to supply the i/o buffers and internal voltage regulator of the device. v s and v dd supplies are separated so that in formation stored in the logic bloc k remains intact in the event of voltage drop outs or disturbances on v s . the system can therefore continue to operate once v s has recovered, without having to resend commands to the device. a rising edge on v dd crossing v dd por triggers an internal power-on reset (p or) to initialize the ic at power-on. all data stored internally is deleted, and the outputs are switched off (high impedance). an electrolytic and 100nf ce ramic capacitors are recommended to be placed as close as possible to the v s supply pin of the device for improved emc performanc e in the high and low frequency band. the electrolytic capacitor must be dimensioned to prevent the vs vo ltage from exceeding the ab solute maximum rating. in addition, decoupling capacitors are recommended on the v dd supply pin. 5.2 operation modes 5.2.1 normal mode the TLE94106EL enters normal mode by setting the en in put high. in normal mode, the charge pump is active and all output transistors ca n be configured via spi. 5.2.2 sleep mode the TLE94106EL enters sleep mode by setting the en input low. the en input has an internal pull-down resistor. in sleep mode, all output transistors are turned of f and the spi register banks are reset. the current consumption is reduced to i sq + i dd_q . 5.3 reset behaviour the following reset triggers have been implemented in the TLE94106EL: v dd undervoltage reset: the spi interface shall not function if v dd is below the underv oltage threshold, v dd poffr . the digital block will be deactivated, the logic contents cleared and the output stages are switched off . the digital block is initialized once v dd voltage levels is above the undervoltage threshold, v dd por . then the npor bit is reset (npor = 0 in sys_diag1 and global status register). reset on en pin: if the en pin is pulled low, the logic conten t is reset and the device enters sleep mode. the reset event is reported by the npor bit (npor = 0) once the TLE94106EL is in normal mode (en = high; vdd > v dd por ).
data sheet 24 1.0 2016-09-08 TLE94106EL general description 5.4 reverse polarity protection the TLE94106EL requires an external reverse polarity pr otection. during reverse po larity, the free-wheeling diodes across the half bridge output will begin to conduct, causing an undesired current flow ( i rb ) from ground potential to battery and excessive power dissipation ac ross the diodes. as such, a reverse polarity protection diode is recommended (see figure 4 ). figure 4 reverse polarity protection v bat outx gnd hsx lsx i rb v bat outx gnd hsx lsx a) b) c s d rp c s2
data sheet 25 1.0 2016-09-08 TLE94106EL half-bridge outputs 6 half-bridge outputs 6.1 functional description the half-bridge outputs of the tle 94106el are intended to drive motor lo ads. these outputs can either be driven continuously or pwm enabled via spi. if the outputs are driven continuously via spi, for example hs1 and ls2 used to drive a motor, then the following suggested spi commands shall be sent: ? activate hs1: bit hb1_hs_en in hb_act_1_ctrl register ? activate ls2: bit hb2_ls_en in hb_act_1_ctrl register 6.1.1 half-bridge operation with pwm enabled all half-bridge outputs of the TLE94106EL are capable of pwm operation. they can ei ther be used to drive an inductive load (e.g. dc brush motor) or optionally a re sistive load (e.g. led). each half-bridge output has been allocated a maximum of three pwm channels with indi vidual duty cycle settings with 8-bit resolution. each channel is further mapped to a maximum of three pwm frequency options, i. e. 80hz,100hz and 200hz. this feature enables a highly flexible pwm operation wh ile driving loads with va rying control profiles. pwm frequency and duty cycle can be changed on demand during pwm operation of the desired half-bridge output. glitches on the pwm output waveform, which may arise as a result of on-demand changes in pwm operation, will be prevented by the internal logic circuitry. when operating with motor loads, active or passive fr ee-wheeling configuration is available via spi to select the speed at which the inductive curr ent can decay over the full-bridge ci rcuit. the default setting is passive free-wheeling. note: active free-wheeling is effectivel y applied if the selected duty cycle corresponds to turn-on times of the hs and the ls, which are longer than the su m of the cross conduction times tdhl + tdlh. table 6 pwm capability and freque ncy selection per half-bridge output control register: hbx_moden (n=0,1) pwm frequency 80hz (control register: pwm_ch_freq_ctrl) pwm frequency 100hz (control register: pwm_ch_freq_ctrl) pwm frequency 200hz (control register: pwm_ch_freq_ctrl) pwm channel 1 pwm_ch1_freq_n (n=0,1) bit ?01 b ? pwm_ch1_freq_n (n=0,1) bit ?10 b ? pwm_ch1_freq_n (n=0,1) bit ?11 b ? pwm channel 2 pwm_ch2_freq_n (n=0,1) bit ?01 b ? pwm_ch2_freq_n (n=0,1) bit ?10 b ? pwm_ch2_freq_n (n=0,1) bit ?11 b ? pwm channel 3 pwm_ch3_freq_n (n=0,1) bit ?01 b ? pwm_ch3_freq_n (n=0,1) bit ?10 b ? pwm_ch3_freq_n (n=0,1) bit ?11 b ?
data sheet 26 1.0 2016-09-08 TLE94106EL half-bridge outputs 6.1.1.1 inductive load an illustration is shown in figure 5 with out1 and out2 driving a dc br ush motor. with this configuration, hs1 is permanently driven while ls2 is driven in pwm operation. hs2 serves to actively free-wheel (fw) the motor current load, reducing the power dissipation of the device. figure 5 pwm operation on out 2 assuming hbx mode = 00 and both hsx and lsx are cons idered off (tri-state). the suggested spi control commands for proper pwm operation are: option 1: the considered output is not put in parallel with another one ? configure the frequency to 00 (pwm is st opped and off) for selected pwm channel ? configure active or passive free-wheeling of the inductive decay current in fw_ctrl register ? assign an appropriate pwm channel for selected half-bridge output in hb_mode_ctrl register ? configure the duty cycle of the selected half-bridge output in pwm_dc_ctrl register ? select the pwm frequency in pwm_ch_freq_ ctrl register to begin the pwm period ? activate the channel to be driven in pwm oper ation: hsn or lsn in the hb_act_ctrl register option 2: outputs controlled by different control registers are put paralleled. this sequence ensures that corresponding hs or ls are activated simultaneously ? configure the frequency 00 (pwm is stopped and off) for selected pwm channel ? configure active or passive free-wheeling of the inductive decay current in fw_ctrl register ? assign an appropriate pwm channel for selected half-bridge output in hb_mode_ctrl register ? configure the duty cycle of the selected half-bridge output in pwm_dc_ctrl register ? activate the channel to be driven in pwm oper ation: hsn or lsn in the hb_act_ctrl register ? select the pwm frequency in pwm_ch_freq_ ctrl register to begin the pwm period careful attention should be paid to the free-wheeling configuration of the half-bridge required to be driven in pwm operation. for example, in the event a high-side channel is activated and assigned a pwm channel, and active free-wheeling is selected, but a frequency mode of ?00? (pwm is stopped and off) is configured in the out 2 out 1 vs hs1 on ls1 hs2 active fw ls2 pwm m1 out 1 out 2 t hbn t cw fw cw fw cw cw fw fw cw = motor clockwise fw = free-wheeling
data sheet 27 1.0 2016-09-08 TLE94106EL half-bridge outputs pwm_ch_freq_ctrl register, then the respective high-side channel wi ll be configured low and the adjacent low-side channel within the half-bridge will be enabled. this is a result of enabling active free-wheeling.
data sheet 28 1.0 2016-09-08 TLE94106EL half-bridge outputs 6.1.1.2 led mode (optional) outputs, out1 and out2, are designed to optionally drive low current loads such as leds. the high-side channels, hs1 and hs2 are equipped with a lower open load threshold detection current and shorter filter time, specifically for low current loads such as leds . see ol_sel_hs1 and ol_sel_hs2 bits in fw_ol_ctrl register. setting hs1 or hs2 in led mode increases the r dson and decreases the open load detection threshold. an illustration is shown in figure 6 with out1 driving an led. with this configuration, hs1 is driven in pwm operation while ls1 is deactivated. figure 6 pwm operation on out 1 assuming hbx mode = 00 and both hsx and lsx are cons idered off (tri-state). the suggested spi control commands are: ? configure frequency 00 (pwm is stopped and off) for selected channel to ensure pwm is off. ? assign an appropriate pwm channel for selected hs1 or hs2 output in hb_mode_ctrl register ? configure duty cycle of selected hs1 or hs2 output in pwm_dc_ctrl register ? activate channel to be driven in pwm operat ion: hs1 or hs2 in the hb_act_ctrl register ? select low current open load detection threshold for hs 1 or hs2 in fw_ol_ctrl register ? select pwm frequency in pw m_ch_freq_ctrl register to begin the pwm period. out 1 hs1 pwm vs
data sheet 29 1.0 2016-09-08 TLE94106EL half-bridge outputs 6.2 protection & diagnosis the TLE94106EL is equipped with an sp i interface to control and diagnose the state of the half-bridge drivers. this device has embedded protective functions which are designed to prevent ic destruction under fault conditions described in the followin g sections. fault conditions are treated as ?outside? normal operating range. protection functions are not design ed for continuous repetitive operation. the following table provides a summary of fault conditions, protec tion mechanisms and recovery states embedded in the TLE94106EL device. table 7 summary of diagnosis and monitoring of outputs fault condition error flag (ef) behaviour error bit: status register output protection mechanism output error state output and error flag (ef) recovery overcurrent latch 1. load er ror bit, le (bit 6) in sys_diag 1: global status 1 register 2. localized error for each hs and ls channel of half-bridge, hbn_hs_oc and hbn_ls_oc bits in sys_diag_2, sys_diag_3 status registers. error output shutdown and latched high-z half-bridge control bits remain set despite error, however the output stage is shutdown. clear ef to reactivate output stage. open load latch 1. load error bit, le (bit 6) in sys_diag 1: global status 1 register 2. localized error for each hs and ls channel of half-bridge, hbn_hs_ol and hbn_ls_ol bits in sys_diag_5, sys_diag_6 status registers. none no state change an open load detection does not change the state of the output. ef to be cleared. temperature pre-warning latch global error bit 1, tpw in sys_diag_1: global status 1 register none no state change not applicable temperature shutdown latch global error bit 2, tsd in sys_diag_1: global status 1 register all outputs shutdown and latched. high-z half-bridge control bits remain set despite error, however the output stage is shutdown. clear ef to reactivate output stage.
data sheet 30 1.0 2016-09-08 TLE94106EL half-bridge outputs power supply failure due to undervoltage latch global error bit 5, vs_uv in sys_diag_1: global status 1 register all outputs shutdown and automatically recovers. high-z half-bridge control bits remain set despite error, however the output stage is shutdown. they will automatically be reactivated once the power supply recovers. ef to be cleared. power supply failure due to overvoltage latch global error bit 4, vs_ov in sys_diag_1: global status 1 register all outputs shutdown and automatically recover. high-z half-bridge control bits remain set despite error, however the output stage is shutdown. they will automatically be reactivated once the power supply recovers. ef to be cleared. table 7 summary of diagnosis and monitoring of outputs (cont?d) fault condition error flag (ef) behaviour error bit: status register output protection mechanism output error state output and error flag (ef) recovery
data sheet 31 1.0 2016-09-08 TLE94106EL half-bridge outputs 6.2.1 short circuit of output to supply or ground the high-side switches are protected against short to ground whereas the low-side switches are protected against short to supply. the high-side and low-side power switches will enter into an over-current condition if the current within the switch exceeds the overcurrent shutdown detection threshold, i sd . upon detection of the i sd threshold, an overcurrent shutdown filter, t dsd is begun. as the current rises beyond the threshold i sd , it will be limited by the current limit threshold, i lim . upon expiry of the overcurrent shutdown filter time, the affected power switch is latched off and the correspondin g error bit, hbn_hs_oc or hbn_ls_oc is set and latched. see figure 7 and figure 8 for more detail. a global load error bit, le, contai ned in the global status register, sys_diag_1, is also set for ease of error scanning by the application soft ware. the power switch remains deactivated as long as the error bit is set. to resume normal functionality of the power switch (i n the event the overcurrent condition disappears or to verify if the failure still ex ists) the microcontroller shall clear the erro r bit in the respective status register to reactivate the desired power switch. figure 7 high-side switch - shor t circuit and overcurrent protection figure 8 low-side switch - shor t circuit and overcurrent protection t dsd_ hs t outn short to gnd short condition on high-side switch | i hs | i i sd_hs i i i lim_hs -i sd_hs i i i lim_hs i on vs t dsd_l s t outn short condition on low-side switch i ls short to supply vs i sd_ls i lim_ls i lim_ls -i sd_ls on vs
data sheet 32 1.0 2016-09-08 TLE94106EL half-bridge outputs table 8 control and status register bit state in the event of an over current condition for an activated power switch register type register name bit before overcurrent during overcurrent after overcurrent bit state bit state bit state control hb_act_ctrl_n hbn_hs_en hbn_ls_en 1 1 1 (corresponding half-bridge deactivated) status sys_diag_1: global status 1 le001 status sys_diag_x where x=2,3 hbn_hs_oc hbn_ls_oc 001
data sheet 33 1.0 2016-09-08 TLE94106EL half-bridge outputs 6.2.2 cross-current in bridge configurations the high-side and low-side po wer transistors are ensured never to be simultaneously ?on? to avoid cross currents. this is achieved by integrating delays in th e driver stage of the power outputs to create a dead-time between switching off of one power transistor and switching on of the adjacent power transistor within the half -bridge. the dead times, t dhl and t dlh , as shown in figure 9 case 3 and figure 10 case 3, have been specified to ensure that the switching slopes do not overlap with each other. this prevents a cross conduction event. figure 9 half bridge outputs switching times - high-side to low-side transition csn 80 % 20 % 80 % 20 % vs vout_ hsx [v ] low-side on delay time t doffh 1) t donl +t dhl 3) t gnd t t vs gnd vout_lsx [ v] 80 % 20 % vs vout_lsx [ v] t donl 2) gnd t 2) delay time ls on without dead tim e ; hs pr eviously off 3) delay time ls on with dead time ; hs previously on hs on ? hs off previous state ? new state ls off ? ls off case 1: delay time high side driver off 1) delay time hs off hs off ? hs off previous state ? new state ls off ? ls on case 2: delay time low side driver on hs on ? hs off previous state ? new state ls off ? ls on case 3: delay time low side driver on with t dhl dead time
data sheet 34 1.0 2016-09-08 TLE94106EL half-bridge outputs figure 10 half bridge outputs switching times- low-side to high-side transition csn 80% 20 % 20 % 80 % high-side on delay time t t donh +t dlh 3) t doffl 1) t t vout _hsx [ v] vs gnd vs gnd vout_ lsx [v] 20 % 80 % t t donh 2) vs gnd vout_hsx [v] 2) delay tim e hs on without dead tim e ; ls previously off 3) hs on delay tim e with dead tim e ; ls pr eviously on hs off ? hs off previous state ? new state ls on ? ls off case 1: delay time high side driver off 1) delay time ls off hs off ? hs on previous state ? new state ls off ? ls off case 2: delay time high side driver on hs off ? hs on previous state ? new state ls on ? ls off case 3: delay time high side driver on with t dlh dead time
data sheet 35 1.0 2016-09-08 TLE94106EL half-bridge outputs 6.2.3 temperature monitoring temperature sensors are integrated in the power stag es. the temperature monitori ng circuit compares the measured temperature to the warning and shutdown th resholds. if one or more temperature sensors reach the warning temperature, the temperat ure pre-warning bit, tpw is set. th is bit is latched and can only be cleared via spi. the outputs stages however remain activated. if one or more temperatur e sensors reach the shut-down temperature threshold, all outputs are latched off . the tsd bit in sys_diag_1: global status 1 is set. all outputs remain deactivated un til the tsd bit is cleared. see figure 11 . to resume normal function ality of the power switch (in the event the overtemperature co ndition disappears, or to verify if the failure still exis ts) the microcontroller sha ll clear the tsd error bit in the status register to reactivate the respective power switch. figure 11 overtemperature behavior v outx t t on high z t j no error t jsd t jw tpw error bit t high low no error tpw is latched, can be cleared via spi output is switched off if t jsd is reached, can be reactivated if tsd bit is cleared tsd er ror bit t high low no error tsd is latched, can be cleared via spi
data sheet 36 1.0 2016-09-08 TLE94106EL half-bridge outputs 6.2.4 overvoltage and undervoltage shutdown the power supply rails v s and v dd are monitored for supply fluctuations. the v s supply is monitored for under- and over-voltage cond itions where as the v dd supply is monitored for under-voltage conditions. 6.2.4.1 v s undervoltage in the event the supply voltage v s drops below the switch off voltage v uv off , all output stages are switched off, however, the logic information rema ins intact and uncorrupted. the v s under-voltage error bit, vs_uv, located in sys_diag_1: global status 1 stat us register, will be set and latched. if v s rises again and reaches the switch on voltage v uv on threshold, the power stages will automa tically be activated. the vs_uv error bit should be cleared to verify if the su pply disruption is still present. see figure 12 . 6.2.4.2 v s overvoltage in the event the supply voltage v s rises above the switch off voltage v ov off , all output stages are switched off. the v s over-voltage error bit, vs_ov, located in sys_diag _1: global status 1 status register, will be set and latched. if v s falls again and reaches the switch on voltage v ov on threshold, the power stages will automatically be activated. the vs_ov error bit should be cleared to verify if the overvo ltage condition is still present. see figure 12 . 6.2.4.3 v dd undervoltage in the event the vdd logic supply decrea ses below the underv oltage threshold, v dd poffr , the spi interface shall no longer be functional and the TLE94106EL will enter reset. the digital block will be initialized and the output stages are switched off to high impedance. the undervoltage reset is released once v dd voltage levels are above the undervoltage threshold, v dd por . the reset event is reported in sys_diag1 by the npor bit (npor = 0) once the TLE94106EL is in normal mode (en = high ; vdd > v dd por ). table 9 control and status register bit state in the event of an overtemperature condition for an activated power switch register type register name bit t j < t jw t j > t jw t j > t jsd t j < t jsd - t jhys bit state bit state bit state bit state control hb_act_ctrl_n hbn_hs_en hbn_ls_en 111 (all outputs are latched off) ?1? (outputs are latched off unless error is cleared) status sys_diag_1: global status 1 tpw 0 1 (latched) 1 (latched) ?0? if error is cleared and t j < t jw , else ?1? status sys_diag_1: global status 1 tsd 0 0 1 (latched) ?0? if error is cleared, else ?1?
data sheet 37 1.0 2016-09-08 TLE94106EL half-bridge outputs figure 12 output behavior during under- and overvoltage v s condition 6.2.5 open load both high-side and low-side switches of the half-bridg e power outputs are capable of detecting an open load in their activated state. if a load current lo wer than the open load detection threshold, i old for at least t dold is detected at the activated switch, th e corresponding error bit, hbn_hs_ol or hbn_ls_ol is set and latched. a global load error bit, le, in the global status register, sys_diag_1: global status 1, is also set for ease of error scanning by the application so ftware. the half-bridge output however, remains activated. the microcontroller must clear the error bit in the respec tive status register to determine if the open load is still present or disappeared. high-side outputs, hs1 and hs2, are sp ecifically designed to detect open load thresholds for led loads. both hs1 and hs2 have a unique and lower open load current threshold and filter time which are configurable via spi in control register, fw_ol_ctrl. during pwm operation, the open load detection is blanked and will not be visible in the status register for power stages used in active free-wheeling output reactivated v uv off v uv on v uv hy t v s v ov hy v ov on v ov off v outx t on high z vs_uv error bit t high low v outx t on high z vs_ov error bit t high low output reactivated spi command : clear sys _diag 1 spi command clear sys_diag1
data sheet 38 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) 7 serial peripheral interface (spi) the TLE94106EL has a 16-bit spi interfac e for output control and diagnostics . this section describes the spi protocol, the control and status registers. 7.1 spi description the 16-bit wide control input word is read via the data input sdi, which is synchronized with the clock input sclk provided by the microc ontroller. sclk must be low during csn fa lling edge (clock polarity = 0). the spi incorporates an in-frame re sponse: the content of the addressed regist er is shifted out at sdo within the same spi frame (see figure 19 and figure 21 ).the transmission cycle begins when the chip is selected by the input csn (chip select not), low active. after the csn input re turns from low to high, th e word that has been read is interpreted according to the conten t. the sdo output switches to tri-st ate status (high impedance) at this point, thereby releasing the sdo bus fo r other use.the state of sdi is shifte d into the input register with every falling edge on sclk. the state of sdo is shifted out of the output register at every rising edge on sclk (clock phase = 1). the spi protocol of the TLE94106EL is comp atible with independent slave configuration and with daisy chain. daisy chaining is applicable to spi device s with the same protocol. writing, clearing and reading is done byte wise. th e spi configuration and status bits are not cleared automatically by the device and theref ore must be cleared by the microcontr oller, e.g. if the tsd bit was set due to over temperature (refer to the respective register descri ption for detailed information). figure 13 spi data transfer timing (note the reversed order of lsb and msb as shown in this figure compared to the re gister description) spi messages are only recognized if a minimum set time, tset, is observed upon rising edge of the en pin ( figure 14 ). 0 0 + 1 2 3 4 5 6 7 8 9 10 15 1 + 0 1 2 3 4 5 6 11 12 13 14 7 8 9 10 15 csn high to low: sdo is enabled. status in formation transferred to output shift register csn low to high: data from shift register is transferred to output functions sdi: will accept data on the falling edge of sclk signal sdo will change state on the rising edge of sclk signal actual status 11 12 13 14 actual data new data new status sdo sdi csn sclk time time time time gef + gef 0 + 1 + lsb msb
data sheet 39 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) figure 14 setup time from en rising edge to first spi communication figure 15 spi data timing 7.1.1 global error flag a logic or combination between global error flag (gef ) and the signal present on sdi is reported on sdo between a csn falling edge and the first sclk rising edge ( figure 13 ). gef is set if a fault condition is detected or if the device comes from a power on reset (por). note: the sdi pin of all devices in daisy chain or non daisy chain mode must be low at the beginning of the spi frame (between the csn falling ed ge and the first sclk rising edge). it is possible to check if the TLE94106EL has detected a fault by reading the ge f without spi clock pulse ( figure 16 ). en spi a) spi message ignored en spi b) spi message accepted t set csn sclk sdi t lead t csnh t lag t sc l kh t sc l kl t pclk t s di_hold sdo t vasd o t en sd o t d issd o 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd t sdi_setup
data sheet 40 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) figure 16 sdo behaviour with 0-clock cycle 7.1.2 global status register the sdo shifts out during the first ei ght sclk cycles the global status register. this register provides an overview of the device status. all failures conditions are repo rted in this byte: ? spi protocol error (spi_err) ? load error (le bit): logical or between open load (ol) and overcurrent (oc) failures ? vs undervoltage (vs_uv bit) ? vs overvoltage (vs_ov bit) ? negated power on reset (npor bit) ? temperature shutdown (tsd bit) ? temperature pre-warning (tpw bit) see chapter 7.7.1 for details. note: the global error flag is a logic or combination of every bit of the global status register with the exception of npor: gef = (spi_err ) or (le) or (vs_uv) or (vs_ov ) or (not(npor) ) or (tsd) or (tpw). the following table shows how failures are reported in the global status re gister and by the global error flag. table 10 failure reported in the global status register and global error flag type of error failure reported in the global status register global error flag spi protocol error spi_err = 1 1 open load or overcurrent le = 1 1 vs undervoltage vs_uv = 1 1 vs overvoltage vs_ov = 1 1 power on reset npor = 0 1 thermal shutdown tsd = 1 1 csn time sclk time global error flag sdo time sdi time high impedance high impedance 0 0
data sheet 41 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) note: the default value (after power on reset) of np or is 0, therefore the de fault value of gef is 1. 7.1.3 spi protocol error detection the spi incorporates an error flag in the global status register (spi_err, bit7) to supervise and preserve the data integrity. if an spi protocol er ror is detected during a given frame, th e spi_err bit is set in the next spi communication. the spi_err bit is set in th e following error conditions: ? the number of sclk clock pulses received when csn is low is not 0, or is not a multiple of 8 and at least 16 ? the microcontroller sends an spi command to an unus ed address. in particular, sdi stuck to high is reported in the spi_err bit ? the lsb of an address byte is not set to 1. in particular, sdi stuck to low is reported in the spi_err bit ? the last address bit token (labt, bit 1 of the address byte, see chapter 7.2 ) in independent slave configuration is not set to 1 ? the labt bit of the last address byte in daisy chain configuratio n is not set to 1 (see chapter 7.3 ) ? a clock polarity error is detected (see figure 17 case 2 and case 3): the incoming clock signal was high during csn rising or falling edges. for a correct spi communication: ? sclk must be low for a minimum t bef before csn falling edge and t lead after csn falling edge ? sclk must be low for a minimum t lag before csn rising edge and t beh after csn rising edge thermal warning tpw = 1 1 no error and no power on reset spi_err = 0 le = 0 vs_uv = 0 vs_ov = 0 npor = 1 tsd = 0 tpw = 0 0 table 10 failure reported in the global status register and global error flag type of error failure reported in the global status register global error flag
data sheet 42 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) figure 17 clock po larity error csn sclk time t bef t beh correct incoming clock signal csn sclk time sclk is high with csn falling edge sclk clock is high with csn rising edge time time time t lead t lag correct clock during csn rising edge case 2: erroneous incoming clock signal csn time case 3: erroneous clock signal during csn rising edge case 1: correct sclk signal
data sheet 43 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) 7.2 spi with independent slave configuration in an independent slave configuration, the microcon troller controls the csn of each slave individually ( figure 18 ). figure 18 spi with independent slave configuration each spi communication starts with one ad dress byte followed by one data byte ( figure 19 ).the lsb of the data byte must be set to ?1 ?.the address bytes specifies: ? the type of operation: read only (op bit =0) or read/ write (op bit = 1) of the configuration bits, and read only (op bit =0)or read & clea r (op bit = 1) of the status bits. ? the target register address (a[6:2]) the last address byte token bit (labt, bit1 of the address byte) must be set to 1, as no daisy chain configuration is used. while the microcontroller sends the ad dress byte on sdi, sdo shifts out gef and the global status register. a further data byte (bit15...8) is allo cated to either configure the half-bridges or retrie ve status information of the TLE94106EL. microcontroller sdi1 tle941xy_1 spi sclk sdo1 csn sdi2 tle941xy_2 spi sclk sdo2 csn sdi3 tle941xy_3 spi sclk sdo3 csn mo mi mclk mcsn1 mcsn2 mcsn3
data sheet 44 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) figure 19 spi operation mode with independent slave configuration the in-frame response char acteristic enables the microcontroller to read the contents of the addressed register within the spi command. see figure 19 . data byte address byte 1 labt = 1 a2 a3 a4 a5 a6 op 0 1 2 3 4 5 6 7 sdi lsb d0 d1 d2 d3 d4 d5 d6 d7 8 9 10 11 12 13 14 15 msb data byte (response ) global status register 0 tpw tsd npor vs_ov vs_uv le spi_ err 0 1 2 3 4 5 6 7 sd0 lsb d0 d1 d2 d3 d4 d5 d6 d7 8 9 10 11 12 13 14 15 msb register content of the selected address time lsb is sent first in spi message
data sheet 45 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) 7.3 daisy chain operation the TLE94106EL supports daisy chain operation with devices with the same sp i protocol.this section describes the daisy chain hardware configuration with three device s from the tle941xy family (see figure 20 ). the master output (noted mo) is connected to a slave sd i and the first slave sdo is connected to the next slave sdi to form a chain. the sdo of the fi nal slave in the chain will be connected to the master input (mi) to close the loop of the spi communication frame. in daisy chai n configuration, a single chip select, csn, and clock signal, sclk, connected in parallel to each slave device , are used by the microcontr oller to control or access the spi devices. in this configuration, the master ou tput must send the address bytes an d data bytes in the following order: ? all address bytes must be sent first: ? address byte 1 (for tle941xy_1) is sent first, followed by address byte 2 (for tle941xy_2) etc,... ? the labt bit of the last address byte must be 1, while the labt bit of all th e other address bytes must be 0 ? the data bytes are sent all together once all addr ess bytes have been transm itted: data byte 1 (for tle941xy_1) is sent first, followed by data byte 2 (for tle941xy_2) etc,... note: the signal on the sdi pin of the first ic in dais y chain (and in non-daisy chain mode), must be low at the beginning of the spi frame (between csn falling edge and the first sclk rising edge). this is because each global error flag in daisy ch ain operation is implemented in or logic. the master input (mi), which is connected to the sd o of the last device in the daisy chain receives: ? a logic or combination of all global error flags (g ef), at the beginning of the spi frame, between csn falling edge and the first sclk rising edge ? the logic or combination of the gefs is followed by the global status registers in reverse order. in other words mi receives first the global status regi ster of the last device of the daisy chain ? once all global status registers are received, mi receives the response by tes corresponding to the respective address and data bytes in reverse order. for example, if the daisy chain consists of three devices with sdo or tle941xy_3 connected to mi, the master receives first th e response byte 3 of tle941xy_3 (corresponding to address byte 3 and data byte 3) followed by the response byte 2 of tle941xy_2 and finally the response byte 1 of tle941xy_1. an example of an spi frame with three devi ces from the tle941xy family is shown in figure 21 .
data sheet 46 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) figure 20 example of daisy chain hardware config uration with devices from the tle941xy family figure 21 spi frame with three devices of the tle941xy family like in the individual slave configuration, it is possible to check if one or several tl e941xy have detected a fault condition by reading the logic or combination of all the global error flags when csn goes low without any clock cycle ( figure 22 ). sdi1 tle941xy_1 spi sclk sdo1 csn sdi2 tle941xy_2 spi sclk sdo2 csn sdi3 tle941xy_3 spi sclk sdo3 csn microcontroller mo mi mcsn mclk mo = sdi1 0 csn time sdi2 = sdo1 global status 1 address byte 2 address byte 3 response 1 data byte 2 data byte 3 gef1 sdi3 = sdo2 global status 2 or gef1/2 address byte 3 response 2 response 1 data byte 3 mi =sdo3 or gef1/2/3 global status 3 global status 1 global status 2 global status 1 response 3 response 2 response 1 sclk 0 8 clock cycles 8 clock cyles address byte 1 address byte 2 address byte 3 data byte 1 data byte 2 data byte 3 labt= 0 labt= 1 labt= 0 8 clock cycles 8 clock cyles 8 clock cycles 8 clock cyles
data sheet 47 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) figure 22 global error flag with ze ro sclk clock cycle in daisy chain consisting only of tle941xy devices note: some spi protocol errors such as the lsb of an address byte is wrongly equal to 0, may be reported in the spi_err bit of another device in the daisy chain (refer to chapter 7.1.3 and chapter 7.7 for more details on spi_err). in this case some devi ces might accept wrong da ta during the corrupted spi frame. therefore if one of the devices in the da isy chain reports an spi error, it is recommended to verify the content of the registers of all devices. 7.4 status register change during spi communication if a new failure occurs after the transf er of the data byte(s), i.e. between the end of the last address byte and the csn rising edge, this failure will be repo rted in the next spi frame (see example in figure 23 ). figure 23 status register change during transfer of data byte - exampl e in independent slave configuration csn time sclk 0 sdi2 = sdo1 gef1 gef1 hiz hiz sdi3 = sdo2 or gef1/2 or gef1/2 hiz hiz mi = sdo3 or gef1/2/3 hiz or gef1/2/3 hiz mo = sdi1 0 sdi 0 csn time sdo global status data byte gef sclk 0 8 clock cycles 8 clock cyles address byte data byte global status data byte gef address byte data byte 8 clock cycles 8 clock cyles hiz hiz new failure detection end of the address byte failure notified in the new spi frame read status byte corresponding to the failure failure is not notified in this spi frame
data sheet 48 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) no information is lost, even if a status register is changed during a sp i frame, in particular during a read and clear command. for example: ? the microcontroller sends a read and clear command to a status register ? the TLE94106EL detects during the tr ansfer the data byte(s) a new faul t condition, which is normally reported in the target status register the incoming clear command will be ignored, so that the microcontroller can read the new failure in the subsequent spi frames. data inconsistency be tween the global status register (see chapter 7.7 ) and the data byte (status register) within the same spi frame is possible if: ? an open load or overcurrent error is dete cted during the transfer of the data byte ? the target status register corres ponds to the new detected failure in this case the new failure: ? is not reported in the global status register of the current spi frame but in the next one ? is reported in the data by te of the current spi frame refer to figure 23 .
data sheet 49 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) figure 24 example of inconsistency between global error flag and status register when a status bit is changed during the transfer of an address byte data byte address byte 1 labt =1 a2 =0 a3 =0 a4 =1 a5 =1 a6 =0 op =0 0 1 2 3 4 5 6 7 sdi lsb x x x x x x x x 8 9 10 11 12 13 14 15 msb response data byte : sys_diag2 global status register 0 tpw tsd npor vs_ov vs_uv le =0 spi_ err 0 1 2 3 4 5 6 7 sdo lsb d0 =0 d1 =1 d2 =0 d3 =0 d4 =0 d5 =0 d6 =0 d7 =0 8 9 10 11 12 13 14 15 msb time overcurrent failure detected on hs of hb 1 during the transfer of the address byte overcurrent failure detected on hs of hb 1 spi frame : read sys _diag2 (oc error of hb 1-4) load error bit (overcurrent or open load ) does not report the new overcurrent failure hb1_hs_oc reports the new overcurrent failure on the hs of hb 1 target status register : oc error of hb 1-4 inconsistency between global status register and target status register data byte address byte 1 labt =1 a2 =0 a3 =0 a4 =1 a5 =1 a6 =0 op =0 0 1 2 3 4 5 6 7 lsb x x x x x x x x 8 9 10 11 12 13 14 15 msb response data byte : sys_diag2 global status register 0 tpw tsd npor vs_ov vs_uv le =1 spi_ err 0 1 2 3 4 5 6 7 lsb d0 =0 d1 =1 d2 =0 d3 =0 d4 =0 d5 =0 d6 =0 d7 =0 8 9 10 11 12 13 14 15 msb target status register : oc error of hb 1-4 new spi frame : e.g. read sys _diag2 (oc error of hb 1-4) consistent information : both load error bit and hb 1_hs_oc report the overcurrent failure detected during the previous spi frame spi frame 1 spi frame 2 (new)
data sheet 50 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) 7.5 spi bit mapping the spi registers have been mapped as shown in figure 25 and figure 26 respectively. the control registers are read/ write re gisters. to set the control register to read, bit 7 of the address byte (op bit) must be programmed to ?0?, otherwise ?1? for write. the status registers are read/clear registers. to clear any status register, bit 7 of the address byte must be set to ?1?, otherwise ?0? for read. figure 25 TLE94106EL spi register mapping note: labt: last address bit token, refer to chapter 7.2 and chapter 7.3 . 15 14 13 12 11 10 9 8 7 65432 1 0 access type read/write 00000labt1 read/write 10000labt1 read/write 11000labt1 read/write 00100labt1 read/write 01100labt1 read/write 11100labt1 read/write 00010labt1 read/write 10010labt1 read/write 01010labt1 read 11001labt1 read/clear 00110labt1 read/clear 10110labt1 read/clear 01110labt1 read/clear 00001labt1 read/clear 10001labt1 sys_diag_2 : op error_1_stat sys_diag_3 : op error_2_stat sys_diag_5 : op error_4_stat sys_diag_6 : op error_5_stat pwm1_dc_ctrl pwm2_dc_ctrl pwm3_dc_ctrl fw_ol_ctrl config_ctrl sys_diag_1 : global status 1 c o n t r o l r e g i s t e r s s t a t u s r e g i s t e r s 8 data bits [d7d0] for configuration & status information 8 address bits [a70] hb_act_1_ctrl hb_act_2_ctrl hb_mode_1_ctrl hb_mode_2_ctrl pwm_ch_freq_ctrl
data sheet 51 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) figure 26 TLE94106EL bit mapping note: labt: last address bit token, refer to chapter 7.2 and chapter 7.3 . 15 14 13 12 11 10 9 8 7 65432 1 0 d7 d6 d5 d4 d3 d2 d1 d0 access type hb_act_1_ctrl hb4_hs_en hb4_ls_en hb3_hs_en hb3_ls_en hb2_hs_en hb2_ls_en hb1_hs_en hb1_ls_en read/write 00000labt1 hb_act_2_ctrl reserved reserved reserved reserved hb6_hs_en hb6_ls_en hb5_hs_en hb5_ls_en read/write 10000labt1 hb_mode_1_ctrl hb4_mode1 hb4_mode0 hb3_mode1 hb3_mode0 hb2_mode1 hb2_mode0 hb1_mode1 hb1_mode0 read/write 11000labt1 hb_mode_2_ctrl reserved reserved reserved reserved hb6_mode1 hb6_mode0 hb5_mode1 hb5_mode0 read/write 00100labt1 pwm_ch_freq_ctrl fm_clk_mod1 fm_clk_mod0 pwm_ch3_freq_1 pwm_ch3_freq_0 pwm_ch2_f req_1 pwm_ch2_freq_0 pwm_ch1_f req_1 pwm_ch1_freq_0 read/write 01100labt1 pwm1_dc_ctrl pwm1_dc_ctrl_7 pwm1_dc_ctrl_6 pwm1_dc_ctrl_ 5 pwm1_dc_ctrl_4 pwm1_dc_ctrl_3 pwm1_dc_ctrl_ 2 pwm1_dc_ctrl_1 pwm1_dc_ctrl_0 read/write 11100labt1 pwm2_dc_ctrl pwm2_dc_ctrl_7 pwm2_dc_ctrl_6 pwm2_dc_ctrl_ 5 pwm2_dc_ctrl_4 pwm2_dc_ctrl_3 pwm2_dc_ctrl_ 2 pwm2_dc_ctrl_1 pwm2_dc_ctrl_0 read/write 00010labt1 pwm3_dc_ctrl pwm3_dc_ctrl_7 pwm3_dc_ctrl_6 pwm3_dc_ctrl_ 5 pwm3_dc_ctrl_4 pwm3_dc_ctrl_3 pwm3_dc_ctrl_ 2 pwm3_dc_ctrl_1 pwm3_dc_ctrl_0 read/write 10010labt1 fw_ol_ctrl fw_hb6 fw_hb5 fw_hb4 fw_h b3 fw_hb2 fw_hb1 ol_sel_hs2 ol_sel_hs1 read/write 01010labt1 config_ctrl reserved reserved reserved reserved reserved dev_id2 dev_id1 dev_id0 read 11001labt1 sys_diag_1 : global status 1 spi_err le vs_uv vs_ov npor tsd tpw 0 read/clear 00110labt1 sys_diag_2 : op error_1_stat hb4_hs_oc hb4_ls_oc hb3_hs_oc hb3_ls_oc hb2_hs_oc hb2_ls_oc hb1_hs_oc hb1_ls_oc read/clear 10110labt1 sys_diag_3 : op error_2_stat reserved reserved reserved reserved hb6_hs_oc hb6_ls_oc hb5_hs_oc hb5_ls_oc read/clear 01110labt1 sys_diag_5 : op error_4_stat hb4_hs_ol hb4_ls_ol hb3_hs_ol hb3_ls_ol hb2_hs_ol hb2_ls_ol hb1_hs_ol hb1_ls_ol read/clear 00001labt1 sys_diag_6 : op error_5_stat reserved reserved reserved reserved hb6_hs_ol hb6_ls_ol hb5_hs_ol hb5_ls_ol read/clear 10001labt1 s t a t u s r e g i s t e r s s t a t u s r e g i s t e r s register name c o n t r o l r e g i s t e r s data bits d7d0 address bits a7a0 c o n t r o l r e g i s t e r s
data sheet 52 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) 7.6 spi control registers the control registers have a read/write access (see chapter 7.5 ): ? the ?por? value is defined by the regist er content after a por or device reset ? the default value of all control registers is 0000 0000 b with the exception of config_ctrl ? the default value of the co nfig_ctrl register is 0000 0011 b ? one 16-bit spi command consists of two bytes (see figure 25 and figure 26 ), i.e. ? an address byte ? followed by a data byte ? the control bits are not cleared or changed automa tically by the device. this must be done by the microcontroller via spi programming. ? reading a register is done byte wise by setting the spi bit 7 to ?0? (= read only). ? writing to a register is done byte wise by setting the spi bit 7 to ?1?.
data sheet 53 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) 7.6.1 control register definition note: the simultaneous activation of both hs and ls switch within a half-bri dge is prevented by the digital block to avoid cross current. if both ls_en and hs_en bits of a given half-bridge are set, the logic turns off this half-bridge. hb_act_1_ctrl half-bridge output control 1 (address byte [op] 000 00[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 hb4_hs_en hb4_ls_en hb3_hs_en hb3_ls_en hb2_hs_en hb2_ls_en hb1_hs_en hb1_ls_en r rw rw rw rw rw rw rw rw field bits type description hb4_hs_en d7 rw half-bridge output 4 high side switch enable 0 b hs4 off/ high-z (default value) 1 b hs4 on hb4_ls_en d6 rw half-bridge output 4 low side switch enable 0 b ls4 off/ high-z (default value) 1 b ls4 on hb3_hs_en d5 rw half-bridge output 3 high side switch enable 0 b hs3 off/ high-z (default value) 1 b hs3 on hb3_ls_en d4 rw half-bridge output 3 low side switch enable 0 b ls3 off/ high-z (default value) 1 b ls3 on hb2_hs_en d3 rw half-bridge output 2 high side switch enable 0 b hs2 off/ high-z (default value) 1 b hs2 on hb2_ls_en d2 rw half-bridge output 2 low side switch enable 0 b ls2 off/ high-z (default value) 1 b ls2 on hb1_hs_en d1 rw half-bridge output 1 high side switch enable 0 b hs1 off/ high-z (default value) 1 b hs1 on hb1_ls_en d0 rw half-bridge output 1 low side switch enable 0 b ls1 off/ high-z (default value) 1 b ls1 on
data sheet 54 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) note: the simultaneous activation of both hs and ls switch within a half-bri dge is prevented by the digital block to avoid cross current. if both ls_en and hs_en bits of a given half-bridge are set, the logic turns off this half-bridge. hb_act_2_ctrl half-bridge output control 2 (address byte [op]100 00[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved reserved hb6_hs_en hb6_ls_en hb5_hs_en hb5_ls_en r rw rw rw rw rw rw rw rw field bits type description reserved d7 rw reserved. always reads as ?0? reserved d6 rw reserved. always reads as ?0? reserved d5 rw reserved. always reads as ?0? reserved d4 rw reserved. always reads as ?0? hb6_hs_en d3 rw half-bridge output 6 high side switch enable 0 b hs6 off/ high-z (default value) 1 b hs6 on hb6_ls_en d2 rw half-bridge output 6 low side switch enable 0 b ls6 off/ high-z (default value) 1 b ls6 on hb5_hs_en d1 rw half-bridge output 5 high side switch enable 0 b hs5 off/ high-z (default value) 1 b hs5 on hb5_ls_en d0 rw half-bridge output 5 low side switch enable 0 b ls5 off/ high-z (default value) 1 b ls5 on
data sheet 55 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) note: refer to chapter 6.1.1 for more information on pwm operation hb_mode_1_ctrl half-bridge output mode control 1 (address byte [op]110 00[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 hb4_mode1 hb4_mode0 hb3_mode1 hb3_mode0 hb2_mode1 hb2_mode0 hb1_mode1 hb1_mode0 r rw rw rw rw rw rw rw rw field bits type description hb4_moden (n = 0,1) d7:d6 rw half-bridge output 4 mode select 00 b no pwm (default value) 01 b pwm control with pwm channel 1 10 b pwm control with pwm channel 2 11 b pwm control with pwm channel 3 hb3_moden (n = 0,1) d5:d4 rw half-bridge output 3 mode select 00 b no pwm (default value) 01 b pwm control with pwm channel 1 10 b pwm control with pwm channel 2 11 b pwm control with pwm channel 3 hb2_moden (n = 0,1) d3:d2 rw half-bridge output 2 mode select 00 b no pwm (default value) 01 b pwm control with pwm channel 1 10 b pwm control with pwm channel 2 11 b pwm control with pwm channel 3 hb1_moden (n = 0,1) d1:d0 rw half-bridge output 1 mode select 00 b no pwm (default value) 01 b pwm control with pwm channel 1 10 b pwm control with pwm channel 2 11 b pwm control with pwm channel 3
data sheet 56 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) note: refer to chapter 6.1.1 for more information on pwm operation hb_mode_2_ctrl half-bridge output mode control 2 (address byte [op]001 00[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved reserved hb6_mode1 hb6_mode0 hb5_mode1 hb5_mode0 r rw rw rw rw rw rw rw rw field bits type description reserved d7:d6 rw reserved. always reads as ?0?. reserved d5:d4 rw reserved. always reads as ?0?. hb6_moden (n = 0,1) d3:d2 rw half-bridge output 6 mode select 00 b no pwm (default value) 01 b pwm control with pwm channel 1 10 b pwm control with pwm channel 2 11 b pwm control with pwm channel 3 hb5_moden (n = 0,1) d1:d0 rw half-bridge output 5 mode select 00 b no pwm (default value) 01 b pwm control with pwm channel 1 10 b pwm control with pwm channel 2 11 b pwm control with pwm channel 3
data sheet 57 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) note: refer to chapter 6.1.1 for more information on pwm operation pwm_ch_freq_ctrl pwm channel frequency select (address byte [op]011 00[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 fm_clk_ mod1 fm_clk_ mod0 pwm_ch3_f req_1 pwm_ch3_f req_0 pwm_ch2_f req_1 pwm_ch2_f req_0 pwm_ch1_f req_1 pwm_ch1_f req_0 r rw rw rw rw rw rw rw rw field bits type description fm_mod_en d7:d6 rw fm modulation enable 1) 00 b no modulation (default) 01 b modulation frequency 15.625khz 10 b modulation frequency 31.25khz 11 b modulation frequency 62.5khz 1) not subject to production test, guaranteed by design. frequency may deviate by 10% pwm_ch3_freq_ n (n=0,1) d5:d4 rw pwm channel 3 frequency select 00 b pwm is stopped and off (default value) 01 b pwm frequency 1 : 80hz 10 b pwm frequency 2 : 100hz 11 b pwm frequency 3 : 200hz pwm_ch2_freq_ n (n=0,1) d3:d2 rw pwm channel 2 frequency select 00 b pwm is stopped and off (default value) 01 b pwm frequency 1 : 80hz 10 b pwm frequency 2 : 100hz 11 b pwm frequency 3 : 200hz pwm_ch1_freq_ n (n=0,1) d1:d0 rw pwm channel 1 frequency select 00 b pwm is stopped and off (default value) 01 b pwm frequency 1 : 80hz 10 b pwm frequency 2 : 100hz 11 b pwm frequency 3 : 200hz
data sheet 58 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) note: refer to chapter 6.1.1 for more information on pwm operation note: refer to chapter 6.1.1 for more information on pwm operation pwm1_dc_ctrl pwm channel 1 duty cycle configurat ion (address byte [op]111 00[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 pwm1_dc_ ctrl_7 pwm1_dc_ ctrl_6 pwm1_dc_ ctrl_5 pwm1_dc_ ctrl_4 pwm1_dc_ ctrl_3 pwm1_dc_ ctrl_2 pwm1_dc_ ctrl_1 pwm1_dc_ ctrl_0 r rw rw rw rw rw rw rw rw field bits type description pwm1_dc_ctrln d7:d0 rw pwm channel 1 duty cycle configuration (bit7=msb; bit0) 0000 0000 b 100% off (default value) xxxx xxxx b parts of 255 on 1111 1111 b 100% on pwm2_dc_ctrl pwm channel 2 duty cycle configur ation (address [op]000 10[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 pwm2_dc_ ctrl_7 pwm2_dc_ ctrl_6 pwm2_dc_ ctrl_5 pwm2_dc_ ctrl_4 pwm2_dc_ ctrl_3 pwm2_dc_ ctrl_2 pwm2_dc_ ctrl_1 pwm2_dc_ ctrl_0 r rw rw rw rw rw rw rw rw field bits type description pwm2_dc_ctrln d7:d0 rw pwm channel 2 duty cycle configuration (bit7=msb; bit0) 0000 0000 b 100% off (default value) xxxx xxxx b parts of 255 on 1111 1111 b 100% on
data sheet 59 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) note: refer to chapter 6.1.1 for more information on pwm operation pwm3_dc_ctrl pwm channel 3 duty cycle configurat ion (address byte [op]100 10[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 pwm3_dc_ ctrl_7 pwm3_dc_ ctrl_6 pwm3_dc_ ctrl_5 pwm3_dc_ ctrl_4 pwm3_dc_ ctrl_3 pwm3_dc_ ctrl_2 pwm3_dc_ ctrl_1 pwm3_dc_ ctrl_0 r rw rw rw rw rw rw rw rw field bits type description pwm3_dc_ctrln d7:d0 rw pwm channel 3 duty cycle configuration (bit7=msb; bit0) 0000 0000 b 100% off (default value) xxxx xxxx b parts of 255 on 1111 1111 b 100% on
data sheet 60 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) note: refer to chapter 6.1.1 for more information on pwm operation fw_ol_ctrl free-wheeling configuration and open load detectio n setting of hs1 and hs2 (address byte [op]010 10[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 fw_hb6 fw_hb5 fw_hb4 fw_hb3 fw_hb2 fw_hb1 ol_sel_hs2 ol_sel_hs1 r rw rw rw rw rw rw rw rw field bits type description fw_hb6 d7 rw hb6 free-wheeling configuration 0 b passive free-wheeling (default value) 1 b active free-wheeling fw_hb5 d6 rw hb5 free-wheeling configuration 0 b passive free-wheeling (default value) 1 b active free-wheeling fw_hb4 d5 rw hb4 free-wheeling configuration 0 b passive free-wheeling (default value) 1 b active free-wheeling fw_hb3 d4 rw hb3 free-wheeling configuration 0 b passive free-wheeling (default value) 1 b active free-wheeling fw_hb2 d3 rw hb2 free-wheeling configuration 0 b passive free-wheeling (default value) 1 b active free-wheeling fw_hb1 d2 rw hb1 free-wheeling configuration 0 b passive free-wheeling (default value) 1 b active free-wheeling ol_sel_hs2 d1 rw hs2 open load detection current and filter time select 0 b high-current mode (default value) 1 b led mode (low current mode) ol_sel_hs1 d0 rw hs1 open load detection current and filter time select 0 b high current mode (default value) 1 b led mode (low current mode)
data sheet 61 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) config_ctrl device configuration control (a ddress byte [op]110 01[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved reserved reserved dev_id2 dev_id1 dev_id0 r rrrrrrrr field bits type description reserved d7:d3 r always reads as ?0? dev_idn d2:d0 r device/ derivative identifier note: these bits can be used to verify the silicon content of the device 000 b tle94112el chip 001 b tle94110el chip 010 b tle94108el chip 011 b TLE94106EL chip 100 b tle94104ep chip 101 b tle94103ep chip 110 b reserved 111 b reserved
data sheet 62 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) 7.7 spi status registers the control registers have a read/clear access (see also chapter 7.5 ): ? the ?por value? of the status registers (content after a por or device reset) and is 0000 0000 b . ? one 16-bit spi command consists of two bytes (see figure 25 and figure 26 ), i.e. ? an address byte ? followed by a data byte ? reading a register is done byte wise by setting th e spi bit 7 of the address by te to ?0? (= read only). ? clearing a register is done byte wise by se tting the spi bit 7 of th e address byte to ?1?. ? spi status registers are not cleared automatically by the device. this must be done by the microcontroller via spi command.
data sheet 63 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) 7.7.1 status register definition note: the le bit in the global status register is read only. it reflects an or combination of the respective open load and overcurrent errors of the half-bridge ch annels. if all oc/ ol bits of the respective high- side and low-side channels are cleared to ?0?, the le bit will be automatically updated to ?0?. sys_diag1 global status 1 (address byte [op]001 10[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 spi_err le vs_uv vs_ov npor tsd tpw reserved r rc r rcrcrcrcrc r field bits type description spi_err d7 rc spi error detection 0 b no spi protocol error is detected (default value). 1 b an spi protocol error is detected. le d6 r load error detection (logic or combination of open load and overcurrent) 0 b no open load and no overcurr ent detected (default value) 1 b open load or overcurrent dete cted in at least one of the power outputs. error latched. fa ulty output is latched off in case of overcurrent vs_uv d5 rc vs undervoltage error detection 0 b no undervoltage on v s detected (default value) 1 b undervoltage on v s detected. error latched and all outputs disabled. vs_ov d4 rc vs overvoltage error detection 0 b no overvoltage on v s detected (default value) 1 b overvoltage on v s detected. error latched and all outputs disabled. npor d3 rc not power on reset (npor) detection 0 b por on en or vdd supply rail (default value) 1 b no por tsd d2 rc temperature shutdown error detection 0 b junction temperature below temperature shutdown threshold (default value) 1 b junction temperature has reached temperature shutdown threshold. error latched and all outputs disabled. tpw d1 rc temperature pre-warning error detection 0 b junction temperature below temperature pre-warning threshold (default value) 1 b junction temperature has reached temperature pre-warning threshold. reserved d0 r bit reserved. always reads ?0?.
data sheet 64 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) sys_diag_2 : op_error_1_stat overcurrent error status of half-bridge ou tputs 1 - 4 (address byte [op]101 10[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 hb4_hs_oc hb4_ls_oc hb3_hs_oc hb3_ls_oc hb2_hs_oc hb2_ls_oc hb1_hs_oc hb1_ls_oc r rc rc rc rc rc rc rc rc field bits type description hb4_hs_oc d7 rc high-side (hs) switch of half-bridge 4 overcurrent detection 0 b no error on hs4 swit ch (default value) 1 b overcurrent detected on hs4 switch. error latched and hs4 disabled. hb4_ls_oc d6 rc low-side (ls) switch of half-bridge 4 overcurrent detection 0 b no error on ls4 switch (default value) 1 b overcurrent detected on ls4 switch. error latched and ls4 disabled. hb3_hs_oc d5 rc high-side (hs) switch of half-bridge 3 overcurrent detection 0 b no error on hs3 swit ch (default value) 1 b overcurrent detected on hs3 switch. error latched and hs3 disabled. hb3_ls_oc d4 rc low-side (ls) switch of half-bridge 3 overcurrent detection 0 b no error on ls3 switch (default value) 1 b overcurrent detected on ls3 switch. error latched and ls3 disabled. hb2_hs_oc d3 rc high-side (hs) switch of half-bridge 2 overcurrent detection 0 b no error on hs2 swit ch (default value) 1 b overcurrent detected on hs2 switch. error latched and hs2 disabled. hb2_ls_oc d2 rc low-side (ls) switch of half-bridge 2 overcurrent detection 0 b no error on ls2 switch (default value) 1 b overcurrent detected on ls2 switch. error latched and ls2 disabled. hb1_hs_oc d1 rc high-side (hs) switch of half-bridge 1 overcurrent detection 0 b no error on hs1 swit ch (default value) 1 b overcurrent detected on hs1 switch. error latched and hs1 disabled. hb1_ls_oc d0 rc low-side (ls) switch of half-bridge 1 overcurrent detection 0 b no error on ls1 switch (default value) 1 b overcurrent detected on ls1 switch. error latched and ls1 disabled.
data sheet 65 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) sys_diag_3 : op_error_2_stat overcurrent error status of half-bridge ou tputs 5 - 8 (address byte [op]011 10[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved reserved hb6_hs_oc hb6_ls_oc hb5_hs_oc hb5_ls_oc r rc rc rc rc rc rc rc rc field bits type description reserved d7 rc reserved. always reads as ?0?. reserved d6 rc reserved. always reads as ?0?. reserved d5 rc reserved. always reads as ?0?. reserved d4 rc reserved. always reads as ?0?. hb6_hs_oc d3 rc high-side (hs) switch of half-bridge 6 overcurrent detection 0 b no error on hs6 swit ch (default value) 1 b overcurrent detected on hs6 switch. error latched and hs6 disabled. hb6_ls_oc d2 rc low-side (ls) switch of half-bridge 6 overcurrent detection 0 b no error on ls6 switch (default value) 1 b overcurrent detected on ls6 switch. error latched and ls6 disabled. hb5_hs_oc d1 rc high-side (hs) switch of half-bridge 5 overcurrent detection 0 b no error on hs5 swit ch (default value) 1 b overcurrent detected on hs5 switch. error latched and hs5 disabled. hb5_ls_oc d0 rc low-side (ls) switch of half-bridge 5 overcurrent detection 0 b no error on ls5 switch (default value) 1 b overcurrent detected on ls5 switch. error latched and ls5 disabled.
data sheet 66 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) sys_diag_5 : op_error_4_stat open load error status of half-bridge outputs 1 - 4 (address byte [op]000 01[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 hb4_hs_ol hb4_ls_ol hb3_hs_ol hb3_ls_ol hb2_hs_ol hb2_ls_ol hb1_hs_ol hb1_ls_ol r rc rc rc rc rc rc rc rc field bits type description hb4_hs_ol d7 rc high-side (hs) switch of half -bridge 4 open load detection 0 b no error on hs4 swit ch (default value) 1 b open load detected on hs4 switch. error latched. hb4_ls_ol d6 rc low-side (ls) switch of half -bridge 4 open load detection 0 b no error on ls4 switch (default value) 1 b open load detected on ls 4 switch. error latched. hb3_hs_ol d5 rc high-side (hs) switch of half -bridge 3 open load detection 0 b no error on hs3 swit ch (default value) 1 b open load detected on hs3 switch. error latched. hb3_ls_ol d4 rc low-side (ls) switch of half -bridge 3 open load detection 0 b no error on ls3 switch (default value) 1 b open load detected on ls 3 switch. error latched. hb2_hs_ol d3 rc high-side (hs) switch of half -bridge 2 open load detection 0 b no error on hs2 swit ch (default value) 1 b open load detected on hs2 switch. error latched. hb2_ls_ol d2 rc low-side (ls) switch of half -bridge 2 open load detection 0 b no error on ls2 switch (default value) 1 b open load detected on ls 2 switch. error latched. hb1_hs_ol d1 rc high-side (hs) switch of half -bridge 1 open load detection 0 b no error on hs1 swit ch (default value) 1 b open load detected on hs1 switch. error latched. hb1_ls_ol d0 rc low-side (ls) switch of half -bridge 1 open load detection 0 b no error on ls1 switch (default value) 1 b open load detected on ls 1 switch. error latched.
data sheet 67 1.0 2016-09-08 TLE94106EL serial peripheral interface (spi) sys_diag_6 : op_error_5_stat open load error status of half-bridge outputs 5 - 8 (address byte [op]100 01[labt]1 b ) d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved reserved hb 6_hs_ol hb6_ls_ol hb5_hs_ol hb5_ls_ol r rc rc rc rc rc rc rc rc field bits type description reserved d7 rc reserved. always reads as ?0?. reserved d6 rc reserved. always reads as ?0?. reserved d5 rc reserved. always reads as ?0?. reserved d4 rc reserved. always reads as ?0?. hb6_hs_ol d3 rc high-side (hs) switch of half -bridge 6 open load detection 0 b no error on hs6 swit ch (default value) 1 b open load detected on hs6 switch. error latched. hb6_ls_ol d2 rc low-side (ls) switch of half -bridge 6 open load detection 0 b no error on ls6 switch (default value) 1 b open load detected on ls 6 switch. error latched. hb5_hs_ol d1 rc high-side (hs) switch of half -bridge 5 open load detection 0 b no error on hs5 swit ch (default value) 1 b open load detected on hs5 switch. error latched. hb5_ls_ol d0 rc low-side (ls) switch of half -bridge 5 open load detection 0 b no error on ls5 switch (default value) 1 b open load detected on ls 5 switch. error latched.
data sheet 68 1.0 2016-09-08 TLE94106EL application information 8 application information note: the following simplified application examples are given as a hint for th e implementation of the device only and shall not be regarded as a desc ription or warranty of a certain functionality, condition or quality of the device. the function of the described circui ts must be verified in the real application. 8.1 application diagram figure 27 application example for dc-motor loads vs2 out 1 out 2 out 3 out 4 m1 m2 m3 out 5 out 6 vdd en sdo sdi csn sclk 60 ? canh 47 nf 60 ? canl can-h can-l split s 1 vbat 1k ? wk 22 nf, 50 v 10 k ? wk c sdo sdi /cs sclk vcc2 vcchscan 10 f int ro v s vbat vbat v s v cc1 vdd 100 nf tle94106 el tle9263 100 nf gnd gnd 10 k ? vdd 3 motors in non-cascaded configuration m1 m2 m3 m4 m5 5 motors in cascaded configuration 10 f 100 nf landing pads for ceramic capacitors at outx series resistors are recommended if vs1/2 of the tle94106 el is protected by an active reverse polarity protection vs1 gnd gnd
data sheet 69 1.0 2016-09-08 TLE94106EL application information figure 28 application exam ple for side mirrors notes on the application example 1. series resistors between the microc ontroller and the signal pins of th e TLE94106EL are recommended if an active reverse polarity protection (mosfet) is used to protect vs1 and vs2 pins . these resistors limit the current between the microcontroller and the device du ring negative transients on vbat (e.g. iso/tr 7637 pulse 1) 2. landing pads for ceramic capacitors at the outputs of the TLE94106EL as close as possible to the connectors are recommended (the ceramic capacitors are not popu lated if unused). these ce ramic capacitors can be mounted if a higher performance in term of esd capability is required. 3. the electrolytic capa citor at the vsx pins should be dimensioned in order to prevent the vs voltage from exceeding the absolute maximum rating . pwm operation with a too low capacitance can lead to a vs voltage overshoot, which results in a vs overvoltage detection. 4. unused outputs are recommended to be left unconnected (open) in the appl ication. if unused output pins are routed to an external connector which leaves the pcb, then these outputs should have provision for a zero ohm jumper (depopulated if unused) or esd protection. in other words, un used pins should be treated like used pins. vs2 out 1 out 2 out 3 out 4 m1 out 5 out 6 vdd en sdo sdi csn sclk 60 ? canh 47 nf 60 ? canl can-h can-l split s 1 vbat 1k ? wk 22 nf, 50 v 10 k ? wk c sdo sdi /cs sclk vcc2 vcchscan 10 f int ro v s vbat vbat v s v cc1 vdd 100 nf TLE94106EL tle9263 100 nf gnd gnd 10 k ? vdd 10 f 100 nf landing pads for ceramic capacitors at outx series resistors are recommended if vs1/2 of the TLE94106EL is protected by an active reverse polarity protection vs1 gnd gnd m2 m3 m4 x-adjustment y-adjustment x-adjustment y-adjustment right mirror left mirror
data sheet 70 1.0 2016-09-08 TLE94106EL application information 5. place bypass ceramic capacitors as close as possible to the vsx pins, wi th shortest connections the gnd pins and gnd layer, for best emc performance
data sheet 71 1.0 2016-09-08 TLE94106EL application information 8.2 thermal application information ta = -40c, ch1 to ch6 are dissip ating a total of 1.2w (0.2w each). ta = 85c, ch1 to ch6 are dissipat ing a total of 0.81w (0.135w each). figure 29 zthja curve for different pcb setups figure 30 zthjc curve 0 10 20 30 40 50 60 70 80 90 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 10000 zth-ja [k/w] time [sec] zth-ja for TLE94106EL 1s0p / 600mm2 / -40c 1s0p / 600mm2 / +85c 1s0p / 300mm2 / -40c 1s0p / 300mm2 / +85c 1s0p / footprint / -40c 1s0p / footprint / +85c 2s2p / -40c 2s2p / +85c 0 2 4 6 8 10 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 zth-jc [k/w] time [sec] zth-jc for TLE94106EL tamb = -40c tamb = +85c
data sheet 72 1.0 2016-09-08 TLE94106EL application information 8.3 emc enhancement in the event the emissions of the device exceed the al lowable limits, a modulation of the oscillator frequency is incorporated to reduce eventual harmonics of the 8m hz base clock. the frequenc ies can be selected based on the resolution bandwidth of the peak detector during emc testing. the selection is achieved by setting the fm_clk_modn bits in the pwm_ch_freq_ctrl register as follows: 00 b : off 01 b : fm clk=15.625 khz 10 b : fm clk=31.25 khz 11 b : fm clk=62.5 khz
data sheet 73 1.0 2016-09-08 TLE94106EL package outlines 9 package outlines figure 31 pg-ssop-24 (plastic/plastic green - dual small outline package) green product (rohs compliant) to meet the world-wide customer requirements for en vironmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e lead-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). pg-ssop-24-4, -9-po v01 1) does not include plastic or metal protrusion of 0.15 max. per side 112 24 13 2) does not include dambar protrusion of 0.13 max. 8.65 0.1 c 0.1 a-b 2x 0.65 0.25 2) m c 0.2 d 24x 0.05 a-b b a index marking c (1.47) 1.7 max. 0.08 c seating plane 0.1 3.9 1) 0.35 x 45 0.25 0.64 0.2 d 6 m 0.2 d +0 -0.1 0.1 stand off +0.06 0.19 8 max. cd 2x 0.1 bottom view 24 1 6.4 0.25 2.65 13 12 0.25 for further info rmation on alternative pa ckages, please visit our website: http://www.infineon.com/packages . dimensions in mm
data sheet 74 1.0 2016-09-08 TLE94106EL revision history 10 revision history revision date changes 1.0 2016-09-08 initial release
trademarks of infineon technologies ag hvic?, ipm?, pfc?, au-convertir?, aurix? , c166?, canpak?, cipos?, cipurse?, cooldp ?, coolgan?, coolir?, coolmos?, coolset?, coolsic?, dave?, di-pol?, directfet?, drblade?, easypim?, econobridge?, ec onodual?, econopack?, econopim?, eicedriver?, eupec?, fcos?, ga npowir?, hexfet?, hitfet?, hybridpack?, imotion?, iram?, isoface?, isopack?, ledrivir?, li tix?, mipaq?, modstack?, my-d?, novalithic?, o ptiga?, optimos?, origa?, powiraudio?, powirstage?, primepack?, primestack?, pr ofet?, pro-sil?, rasic?, real 3?, smartlewis?, solid flas h?, spoc?, strongirfet?, supirbuck?, tempfet?, trenchstop?, tricore?, uhvic?, xhp?, xmc?. trademarks updated november 2015 other trademarks all referenced product or service names and trademarks are the proper ty of their respective owners. edition 2016-09-08 published by infineon technologies ag 81726 munich, germany ? 2016 infineon technologies ag. all rights reserved. do you have a question about any aspect of this document? email: erratum@infineon.com important notice the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("beschaffenheitsgarantie"). with respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. in addition, any information given in this document is subject to customer's comp liance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of infineon technologies in customer's applications. the data contained in this document is exclusively intended for technically trained staff. it is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements products may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. except as otherwise explicitly approved by infineon technologies in a written document signed by authorized representatives of infineon technologies, infineon technologies? products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. please read the important notice and warnings at the end of this document

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